Project Title A Low Power CIC Filter For Delta-Sigma ADC
Student Name Siva Kumaaran a/l Palanisamy
Supervisor Ir. Dr. Lee Lini
Year of Completion 2018
Description This project presents a power-optimized third-order cascaded integrator comb (CIC) Filter for the Delta-Sigma (Δ-Σ) Analog-to-Digital Converter (ADC). The CIC Filter refers to a type of decimation filter used in ADC to remove quantization error caused by the modulator. It also occupies less area, when compared to other decimation filter, due to the absence of multiplier. In Δ-Σ ADC, the power consumption is mainly driven by the decimation filter. Hence, careful optimization of the decimation filter is necessary to design an ADC with low power.

In this project, a True Single Phase Clocked (TSPC) D-Flip Flop, which is made up of split-output latches, was applied as the register, instead of conventional D-Flip Flops. The proposed design displayed a significant reduction in power consumption, propagation delay and the overall size. The proposed architecture was realized by using the CMOS 0.13 μm technology.


Figure 1: Block diagram of first order CIC filter.

Results / Conclusion The third-order 13-bit CIC Filter with an oversampling ratio of 32 for Δ-Σ ADC had been designed successfully in this project. The decimation filter consists of coder circuit, integrator, differentiator, clock divider, and down-sampling register. The CIC filter was implemented by using CMOS 0.13 μm technology. It used only 47.98 μW of power from 1.5 V supply voltage. A delay of 993.31n is recorded from the CIC Filter. The layout for 1-bit third-order CIC Filter is also realized with the size of 105.580 ◊ 29.930 μm2. The usage of positive-triggered TSPC D-Flip Flop in the integrator and differentiator substantially contributed to reduce power consumption of the decimation filter. Moreover, lower propagation delay is recorded when using TSPC D-Flip Flop compared to the conventional one. Lastly, the size of the CIC Filter is smaller as TSPC D-Flip Flop has only eight transistors.


Figure 2: Complete block diagram of third order CIC Filter with 17-bits.

Table 1: Comparison of Power Dissipation

D Flip-FlopPower Dissipation
Before (Conventional D Flip-Flop)3.0568 mW
After (TSPC D Flip-Flop)47.9769 μW

Table 2: Comparison of Delay

D Flip-FlopDelay
Before (Conventional D Flip-Flop)4.93 ms
After (TSPC D Flip-Flop)993.31 ns


Figure 3: Layout of 1-bit CIC Filter.

 

Project Title High Speed CMOS Comparator in ADC For IoT Applications
Student Name Balraj Pillai a/l Tharumalingam
Supervisor Ir. Dr. Lee Lini
Year of Completion 2018
Description A high speed and low powered comparator design is presented and the behavior of the proposed comparator shows double the improvement of performance matrix in comparison with the conventional double-tail comparator. Comparator architecture design consists of a double-tail topology comparator, a cross-coupled dynamic NOR-gates and output inverters. Direct advantages of a dynamic NOR-gate compared to the static NOR-gate is that it provides faster gates, allowing more logic per cycle with less delay. The cross-coupled dynamic NOR-gates represent a structure of SR latch, but with clocked input control, in which provides a refreshed clock signal into the circuit. The dynamic SR latch offers highly reduced delay, but with a tradeoff of greater noise sensitivity, more power dissipation and more design time. A special characteristic of the dynamic NOR-gate is that it has a keeper transistor, which offers stability of the SR latch in a whole. The PMOS keeper supplies enough current and maintains the voltage at output node, q/qbar, so that the output does not flip erroneously. In the context of stability, the static SR latch may permit better range of signal integrity.


Figure 1: Block Diagram of Double-tail Comparator

Results / Conclusion In essence, a high speed and low powered dynamic comparator has been designed on an Electronic Design Automation (EDA) platform known as Mentor Graphics using Silterra 0.13 μm CMOS technology. This design is highly anticipated to be used for future ADC structures that can be integrated with IoT applications for reasons that are stated below.

The proposed comparator in post-layout simulation serves a low total power consumption of 102 nWatts at 1.0 V power supply and 100 MHz clock frequency. Figure 2 shows where outn and outp shows two values of delay 194.912 ps and 226.4430 ps. However, the average of the delays is taken to obtain the significant value of propagation delay of the comparator 210.6775 ps. The propagation delay from post-layout simulations is 210.67 ps which gives a speed of 4.74 GHz, whereas pre-layout simulation shows 145.97 ps. Power-delay-product of design in post-layout gives 0.0146 fW/s.


Figure 2: Propagation Delay of Proposed Comparator

Another aspect of the design is the temperature sensitivity in which is found to be very small at 0.223 ps/øC. The value propagates temperature robustness of the comparator, in which is an added advantage in practical world. However, the typical response for temperature sweep remains the same, increasing linearly.

The variation of process corners of MOS devices remains significantly large in terms of propagation delay. This largely gives an overview anticipation of any physical defect on MOS device can result in poor performance, in other words, larger delay and possibly higher power consumptions.


Figure 3: Propagation Delay versus Supply Voltage for Varying Input Voltage Difference


Figure 4: Propagation Delay versus Supply Voltage for Varying Common-mode Voltage

As generally unstable as comparator designs are, the two cross-coupled dynamic NOR-gates offers signal stability and integrity to work on very small electrical properties up to 39.0625 μV on input voltage difference, ΔVIN. Whereas the common-mode voltage has higher impact onto the performance of the comparator as shown in Figure 4. Figure 5 below illustrates the layout design with total die area of 577.67 μm2. In conclusion, the proposed design is successful in terms of operation, functionality and performance.


Figure 5: Complete Layout Design

 

Project Title Fundamental limitation of GaN-based Gunn Diodes for THz Signal Generation
Student Name Lee Wen Zhao
Supervisor Prof. Dr. Ong Duu Sheng
Year of Completion 2017
Description A fundamental limitation for maximum generated sub-THz power exists for conventional Gunn oscillators like GaAs and InP-based diodes. GaN, a wide-bandgap semiconductor with its high threshold electric field in the negative differential resistance (NDR) condition is a suitable material for developing high power THz source. This project aims to study the theoretical limit of operating frequency in GaN-based Gunn diodes. A physical model based on Monte Carlo method will be developed to model the high field electron transport in Zinc-blende and Wurtzite GaN bulk structure. The Monte Carlo model will employ an analytical-band structure to represent the conduction band and include all scattering mechanisms in GaN. This model will be coupled with the Poisson solver to develop an ensemble self-consistent Monte Carlo model, capable of simulating the current oscillation in Gunn diode. The upper operating frequency limits in GaN-based Gunn diodes will be studied for different doping concentrations and device lengths.


Figure 1: Simulated GaN n++n-n+n++ Gunn diode device structure

Results / Conclusion Figure 2 shows the Monte Carlo simulated current oscillation in Gunn diode biased at 55V. The current oscillation frequency is about 200 GHz. The formation and propagation of high field domain in the active region, known as Gunn Effect is shown in Figure 3 and 4. Simulations of different device structures are carried out and analysed, finding that a GaN diode with 500nm transit region exhibits operating frequency of 460GHz with power efficiency of about 1% is predicted.


Figure 2: The electric current in Gunn diode at applied voltage of 55V


Figure 3: The electron charge density at different simulation times


Figure 4: The corresponding electric field profile of Figure 3 in the simulated Gunn diode

 

Project Title A Visual-based Automated Whiteboard Cleaner
Student Name Tey Jian Zhong
Supervisor Wong Hwee Ling
Year of Completion 2017
Description A robotic whiteboard cleaner was designed and developed. The aim is to able to automatically detect markings location and clean the markings based on the visual inputs. The mechanical structure of the robot is built based on Cartesian robot system in order for the duster to travel to specific x-y coordinates on the whiteboard (see Figure 1).

When the program on the computer is launched, the robot starts to calibrate its position to a default home position. Once the calibration is completed, the image captured from the webcam undergoes image processing to identify locations of the markings. After the image processing stage, the location of the ink marking is sent to the microcontroller through the serial protocol. Once the robot receives the serial command package, the robot cleaner executes the cleaning profile and cleans the ink marking. If there is no ink marking left on the whiteboard, the whiteboard robot cleaner returns to the home position.


(a)


(b)

Figure 1: Mechanical structure of whiteboard robot cleaner.
(a) Frontal view; (b) Side view
Results / Conclusion The experimental setup is shown in Figure 2. The whiteboard has a dimension of 60 cm ◊ 45 cm. The overall performance of the robot cleaner was tested by cleaning actual ink marking on the whiteboard. The markings detected are highlighted in a green box and the center of the box is marked as the red dot (see Figure 3). The robotic cleaner is able to clean markings at different locations on the whiteboard. Cleaning performance for different types and sizes of markings were also documented. The time taken to clean the marking is based on the number of markings, the size of a marking and its location on the whiteboard. If the marking is located further away from the home position, the longer it will take to clean the marking. If the marking is smaller, it takes a shorter time to complete the cleaning. For instance, a marking with the size of 78 cm2 requires an average 2.02 minutes of cleaning time. In contrast, a marking of 13.5 cm2 requires an average of 28.96 seconds only.


Figure 2: The experimental setup


Figure 3: Markings detected on the whiteboard

 

Project Title Context-Aware Shopping Cart
Student Name Tan Kang Zhe, Soh Meng Wah
Supervisor Tan Wooi Haw
Year of Completion 2013
Description This project aims to develop an Intel Atom processor-based context aware shopping cart to enhance the use of information technology in mobile physical environment. The purpose of this shopping cart (trolley) is to support shopping through context-awareness with the integration of a display unit which shows the relevant advertisements of promotional items and other information depending on the current location of the shopping cart. This system could potentially boost consumersí shopping experience with electronic advertisements as well as providing them with first hand-info when they are entering different sections of the shopping mall.

Results / Conclusion The system is able to help the retailers in promoting their products while assisting the consumers to efficiently navigate through the shopping mall. Hence, this system would be able to serve the community by implementing the context awareness concept.

 

Project Title A Road Lane Departure Warning System
Student Name Beh Ai Di,Tan Teck We
Supervisor Wong Hwee Ling
Year of Completion 2013
Description An automated Lane Departure Warning System (LDWS) provides signal if a vehicle is exiting a road lane. There are a growing number of car manufacturers that manufacture vehicles with build-in LDWS. However, most vehicles on the road as of today do not have the feature. Design and development of an electronic warning unit and integration scheme of a road lane departure algorithm onto that unit was presented in this project (see figure below). An Android smartphone processes real-time images for the road lane detection. The result is sent to the electronic warning unit via Bluetooth communication. The electronic unit runs mainly on a microcontroller and can provide visual, audio and tactile warning to a human driver. Warning protocol for different operating conditions was evaluated and proposed.

Results / Conclusion The Android application for road lane detection is developed using the Eclipse IDE, where several tools such as the Android SDK, Android NDK and Java Development Kit (JDK) were integrated together. The image processing algorithm was written in C++ with the utilization of OpenCV library while the foreground of the phone application interface was written in Java. 2714 video frames that were used to evaluate the road lane detection algorithm consist of several environment classes ranging from clear daylight to adverse weather condition, such as heavy rain during day and night (see figure below). The highest accuracy of 93.2% was achieved via cloudy daytime class. When the environment is sunny, the detection rate drops as the image appears brighter and the contrast between the road line and road is reduced. The lowest accuracy attained is 49.5% where the frames were captured at rainy daytime environment. The road lane detection rate during raining night time environment is 83.9% as the road line marking appears to have greater contrast than the road itself when the headlights of the vehicle hits on it. The average frame rate computed on the dual-core 1.4GHz ARM cortex-A9 smartphone is 3.683 frames per second with an original image resolution of 1280◊720 pixels. The device runs on Android 4.0.4 operating system. Preview of the result on phone screen takes up unnecessary processing time and can be eliminated in actual application.

 

Project Title Design of Multiple Green Energy Sources Powered Wireless Repeater
Student Name Ooi Lay Ping
Supervisor Pang Wai Leong
Year of Completion 2013
Description The objective of this project is to design a green wireless repeater that consists of two green energy sources, such as solar and thermal energies. Solar panel and thermoelectric module are used to harvest the solar and thermal energies respectively. The solar panel collects the photon from the sunlight and converts to electricity. Thermoelectric module converts the waste heat from the industrial furnace, hot spring and heat from the sun to electricity. Both powers are used to charge the sealed lead acid rechargeable battery through a charging controller.To avoid overcharging and undercharging, a charging controller was proposed in this project. A buck converter and boost converter were implemented in this project. Both converters are used to step up the power from the thermoelectric module and step down the voltage from the sealed lead acid rechargeable battery. A battery level indicator was used to indicate the voltage level of the lead acid battery. In this project, a wireless repeater is used as the load that powered by the green energies.The design proposed was analyzed through simulation. Experimental results were obtained from the design prototype. Functional verification was carried out between the simulation and the experimental results and it shown that the prototype is working as per expectation.

Results / Conclusion The main purpose of this project is to design a prototype that reduces the pollution and environment friendly by using the green energies. The benefits of this project are lower cost for long run, high portability and lower maintenance.The objective of the project is to design a multiple green energy sources to power up a wireless repeater. It consists of two parts. First is solar panel that used to charge the rechargeable battery through the charging controller. Then second part is used the thermoelectric module to charge the rechargeable battery through a charging controller. The rechargeable battery is used to power up the wireless repeater. The buck converter is used to step down the voltage from rechargeable battery to wireless repeater.Theoretically, analysis had been carried out in this project to identify the efficiency of the design. The hardware prototype is realized perform experimental test and performance. The experiment results had been obtained, and the results are tally with the generated through simulation. Functional verification and performance analysis had been carried out through simulation.

 

Project Title Discrete Class A OP-AMP
Student Name Ooi Tze Yang
Supervisor Lee Seng Siong
Year of Completion 2012
Description A discrete operational amplifier (op-amp) operating in Class A is designed and proposed. The advantages of discrete op-amps can be traced to using Class A operation in every internal stage of the op-amp. To investigate the benefits of Class A operation, the NE5534, a monolithic integrated circuit (IC) op-amp is modified by replacing its internal Class AB output stage with a heavily biased Class A discrete output stage. The performance of the NE5534 is compared against the modified NE5534; using data measurements acquired using an audio analyzer.

Results / Conclusion It is found that when loaded with 600 Ohms at 2 Vrms, the NE5534ís output stage leaves Class A region and operates in Class AB. On the contrary, the modified NE5534 remains steady at Class A operation. Comparing both circuits, at 600 Ohms, the modified NE5534 offers a reduction of 75.8% for Total Harmonic Distortion (THD %) and 42.31% for Intermodulation Distortion (IMD %) over the regular NE5534. This proves that using Class A operation enables a significant reduction in distortion. Next, to further investigate the advantages of a discrete op-amp, a discrete op-amp is designed and built. The circuit is designed with its every internal stage operating in Class A operation. By using discrete components, the capacity of heat dissipation increases. Thus, deep Class A operation running in high quiescent current can be realized. The size is also designed to be small with a horizontal size of 10x10mm, complying with the size standard of a DIP-8 package IC op-amp. The performance is measured using an audio analyzer and it is found that comparing to NE5534, the THD % improves by 81.67%, while the IMD % improves by 78.46%. In both experiments, using Class A operation substantially improves the performance figures of the op-amp. In conclusion, a properly designed discrete op-amp that fully utilizes the benefits of Class A operation is superior to monolithic IC op-amps for audio purposes.

 

Project Title Two-Wheeled Balancing Robot
Student Name Lim Chia Syan
Supervisor Lo Yew Chiong
Year of Completion 2011
Description This project involves designing and constructing a two-wheeled balancing robot system. Due to unstable nature of the system, the two-wheeled balancing robot is proven to be an excellent test platform for sensor fusion utilizing Kalman Filter to obtain an accurate estimate of tilt angle and its derivative for the robot through the measurement of an accelerometer and a gyroscope. Besides, the two-wheeled balancing robot also served as a tremendous test platform for a few of modern control theories implementation. In this project, two linear control systems which are Linear Quadratic Regulator Controller and Pole-Placement Controller are investigated and applied in the balancing algorithms to examine the suitability and performance of the controller itself.

Results / Conclusion The Kalman Filter used in the project is successfully tuned where the filtered results show great response while being able to eliminate the noises exist in the raw readings from both the gyroscope and accelerometer. Besides, the LQR controller implemented by taking into consideration all the four state variables shows a very promising and optimal control system for the two-wheeled balancing robot. The balancing algorithm employed in this project effectively allows the robot to balance by its own. However, fine-tuning and more simulations are still required in order to achieve better balancing response.

 

Project Title Distributed Thermal Monitoring, Logging and Control with LabVIEW for Verification and Validation Testing
Student Name Kelvin Tang Seng Ban
Supervisor Mohd Haris Lye Abdullah
Year of Completion 2011
Description This project consists of an automated real time system that provides temperature monitoring and logging, and a standalone software for remote test chamber control. The system user interface can be accessed remotely with a computer connected within the local area network.

Results / Conclusion The system temperature measurement accuracy is tested to be 99.89%. The system is tested for 24 hours monitoring and logging without error and provided an accurate data log. This project is a success where all key requirements are met.

 

Project Title Hardware Gesture Recognition Algorithm for Real Time FPGA Implementation
Student Name Lee Sue Han
Supervisor Cheong Soon Nyean
Year of Completion 2011
Description This project describes the design and implementation of the hand gesture recognizer system for controlling the hardware appliance in real time. The FPGA based implementation of hand tracking system includes the image preprocessing state and feature extraction state that consists of bounding box and Center-Of-Mass based computation. Through the features extraction state, the object's Center-Of-Mass and bounding box attributes are extracted and to be applied for gesture sign classification. The main modules in the system employs exploit the parallelism architecture of the FPGA to achieve real time processing. The hardware design is categorized into 4 modules which are the camera, image processing and control unit, display unit and the hardware appliance. The FPGA fabric on Altera DE2 board and does all the image processing and control. The flow of the image processing described can be seen in the block diagram below.

The CMOS Sensor Data Capture will take in raw picture from the Image Sensor and feed into the Bayer Color Pattern Data to 30-bit RGB conversion module and finally stored in the SDRAM via the SDRAM controller. In image preprocessing state, the data read out from the SDRAM will be going through segmentation process where the target object is segmented and other unused images are filtered out. After that, the Feature Extraction Module extracts the required features to recognize the hand. Finally, the VGA controller sends the color information to the display unit. The display unit will show the result of hand tracking system. The information of object's Center-Of-Mass and bounding box attributes generated by feature extraction module is sent to the gesture sign classification module where the hand gestures are recognized in order to interact with the hardware appliance. The system created is used to test on controlling a RC car. The transmitter circuit of the RC car controller is connected to the FPGA with the aid of ribbon cable and expansion header. The figure below shows the interconnection between hardware modules.

Results / Conclusion The system met the objective of the project that bridges the gap between the traditional physical hardware devices and the user while supporting real time processing. However, since the project is using camera-based gesture recognition, it has serious spatial limitation. A certain distance required for the camera to recognize the user's gesture. Experiments have been done to test the reliability of the system and it shows that not only the light intensity or brightness affects the target object captured but also the placement of the light source with respect to the user's gesture and the camera. The project won first prize at Innovate Malaysia Design Competition 2011 for the Altera track.

 

Project Title Navigation of a Mobile Robot for Remote Indoor Operation
Student Name Kenny Yeoh Ju Min
Supervisor Wong Hwee Ling
Year of Completion 2011
Description The project "Navigation of a Mobile Robot for Remote Indoor Operation" enables control of a "Remote Navigable Robot" (RNR) through the Internet and allows visual feedback from the RNR to the user. It uses the Linux operating system on an ARM920T based single-board computer acting as a webserver which implements a Java Servlet. A PIC18F4550 microcontroller is used for low level control of the RNR's motor and speed. Visual feedback is provided by a UVC Webcam and wireless connectivity is achieved using a Wi-Fi USB dongle. Remote control is provided in a standard web browser with JavaScript capability. The RNR can be operated entirely on batteries while maintaining full functionality and is able to traverse common indoor terrains. The control interface is supported in various browsers and platforms but require significant processing power to stream the video. The RNR provides with a wide range of application possibilities.

Results / Conclusion The weight of the RNR is estimated to be approximately 2.5 kg. The ground clearance of the RNR is approximately 2 cm. The RNR is tested to be able to run on different types of tiles ranging from smooth marble to rough textured tiles. It is also able to run on wooden parquet floors. The maximum speed of the RNR was measured to be 0.46 ms-1. The RNR can form a circle with a radius of approximately 0.3 m. The RNR can be controlled remotely through web server using mouse or game controller. The operator uses the video stream displayed on the webpage to see the robot's view. The control interface for web browser was implemented as HTML standard webpage. It was tested on Windows 7 using Microsoft Internet Explorer 9, Mozilla Firefox 4 and Google Chrome 10. Google Chrome was also tested using Ubuntu 10 Linux version. Control buttons and video streaming works as expected. However, the use of JavaScript to refresh the video stream causes the CPU utilization of the browser to increase significantly. CPU speed also plays an important role to run the web application. The game controller interface was done using MFC application. Input from the game controller was obtained using Direct Input and the analogue joystick on the game controller was used to control the direction and speed. Hence, the game controller can be used instead of using the mouse to remotely control the RNR.

 

Project Title Controller Design for a Cooling System with LABVIEW Implementation
Student Name Tay Hui Yen
Supervisor Dr. Tan Ai Hui
Year of Completion 2011
Description The objective of the project is to design a discrete Proportional-Integral-Derivative controller for a cooling system and implement it using LABVIEW software. A reduced order model for the cooling system with duty ratio of a Peltier module as input and chamber temperature as output is first identified. The performance of the reduced order model in modeling the actual system is evaluated. A discrete PID controller is designed to control the reduced order model of the system. The controller is built using LABVIEW software. The performance of the controller is evaluated both through simulation and real experimentation


Peltier cooling system setup

Results / Conclusion From the simulation and experimental results, it is observed that the operating range of the peltier cooling system has been well defined. The operating region for this peltier is 4įC to 8įC. For the use of Kp larger than 10, the system will experience large overshoot and becomes unstable. For the Ki smaller than a certain value, the performance of the peltier is greatly affected. To minimise the overshoot, the magnitude of disturbance can be reduced. From the overall observation of the performance of the PID of the peltier cooling system, it is concluded that a good PID controller can be derived from a good mathematical model of the peltier system. This shows that system identification is a crucial step to provide a good set of parameters for the design of the parameters of the PID controller.


Step response of a PID controller with derivative filter (solid line),
normal Proportional-Integral-Derivative controller (dashed line) and a
P-controller (dotted line) tuned using Internal Model Control algorithm

 

Project Title Design of Software for Modelling Tube Furnace Systems
Student Name Kevin Lim Khai-Wern
Supervisor Dr. Tan Ai Hui
Year of Completion 2010
Description The objective is to design a software for modelling and simulating furnace systems. A tube furnace system is a heating system made from a ceramic tube, heated by coils of heating elements around it. It has many applications in practice, for example in the semiconductor and metallurgy industries. In this project, a multizone furnace is to be modelled. A user-friendly software is to be developed where the user can simulate the static and dynamic thermal behaviour of such a furnace. The thermal behaviour is dependent on the heating power, thermal properties of the materials used in the construction and the geometry of the furnace. These should be used as inputs to the simulation software. The effects of conduction and radiation should be included in the model. Such a model will be useful for use in subsequent controller design.
Results / Conclusion A user-friendly software is designed using JAVA. The computation done is based on finite element analysis. It has the following functionalities:
  • Allows user input of the furnace parameters.
  • Allows the calculation of temperature along the length and radius of the furnace.
  • Simulates the changes of temperature against time using colour to represent temperature.
  • Allows the user to save the output to a folder.

 

Project Title (1) Solar-powered wireless sensor node: Design of the sensing system and energy-efficient wireless communication
(2) Solar-powered wireless sensor node: Harnessing and storage of solar energy, and user interface design
Student Name (1) Yap Yung Pin
(2) Jonathan Lourdes a/l Luruthusamy
Supervisor Foo Yee Loo
Year of Completion 2009
Description In this project, a solar-powered wireless sensor node is designed and constructed for the purpose of landslide prediction. This low-cost node is built from off-the-shelf products: an accelerometer that functions to sense the degree of tilt due to soil movement, a wireless transceiver that sends the tilt data to a host, and a solar power harnessing circuit that powers the node. A network of such nodes, when deployed in the field, will form an early warning system for landslides.

Results / Conclusion The design and construction of the solar-powered wireless sensor nodes have been completed. A simple landslide prediction system is built from these nodes. We have simulated a miniature landslide to demonstrate that the system is functional. In the experiment, when the soil movement caused the node to tilt more than a predetermined threshold, a SMS alert was sent out to warn the relevant personnel on a possible landslide.

 

Project Title A Smart Mobile Robot
Student Name Cham Chin Leei
Supervisor Dr Tan Ai Hui
Year of Completion 2008
Description The project studied the Smart Mover, a multipurpose robotic platform developed to assist the physically handicapped in indoor and outdoor movements. The Smart Mover is designed to overcome stairs, steps, harsh landscape conditions, and other unpredictable obstacles where wheeled and tracked robots are known to have difficulties. Smart Moverís unique chassis design enables it to achieve extraordinary stability on uneven terrains and during stair-climbing. The mechanically simple design and use of commercially available components makes Smart Mover easily maintainable. The key challenge is to maintain loads carried on the platform in stable condition while Smart Mover is moving around. Focus is placed on how Smart Mover climbs up and down staircases as this offers one of the most challenging problems to any mobile robot. Smart Mover's special chassis is designed to hold four mono-axis linear actuator legs which are extendable in one axis, and four bi-axis legs which are extendable in two axes. The Smart Mover currently uses a basic motion profile with constant velocity and torque while the leg is being extended. Motion of this type would cause the robot to lose its balance when the two parallel legs are required to extend in different height. This issue is more significant when the robot is moving on high speed. One possible solution is to utilize highly sensitive pressure sensor on the base of the linear actuator. Independent feedback system is also being recommended in each part of sensor and feedback control so that the robot can react to real time input signal and hence achieve the a higher level of stability.

Results / Conclusion A prototype for the Smart Mover is constructed. The experiments carried out considerably verified the performance characteristics of stair climbing and forward motion for the Smart Mover. Future work will concentrate on simultaneously improving the speed and stability of the robot.

 

Project Title Identification and Control of an Electric Resistance Furnace
Student Name Lau Sook Yen
Supervisor Dr Tan Ai Hui
Year of Completion 2008
Description In this project, identification of an electric resistance single zone furnace is described. Experimental data are collected and used for estimating the parameters of an electric resistance furnace. The modeling using second order linear model is considered. The transfer function is simulated using Matlab and a proportional-integral-derivative (PID) controller tuned using Integral of Squared Time Weighted Error (ISTE) tuning rule controller is designed. This controller is implemented on the real furnace using VHDL coding. As the thermal behavior is dependent on the heating power, the heating power is controlled by pulse width modulation (PWM) technique. A desired temperature setpoint is used as input to this control system. This project also includes software design using VHDL modeling, simulation, synthesis and FPGA realization. This work is done by performing the complete design flow to design, model and simulate furnace systems using VHDL languages. Altera Cyclone II FPGA Starter Development Kit, DE1 board is used. The final resulting controller is synthesizable and this controller can used to control the real furnace.

Results / Conclusion A furnace system has been identified in open loop. It was found that a linear second order transfer function between input duty ratio and output temperature can describe the dynamics of the furnace relatively well. Based on the estimated transfer function, the model is simulated in Matlab and a suitable controller is designed which gives a good overall performance in terms of overshoot and settling time. The controller is implemented using Altera DE1 Board using VHDL coding. The coding allows the actual temperature of the furnace to be detected. This temperature is then used in a feedback loop to adjust the appropriate value of the input duty ratio in order to achieve the desired setpoint. The hardware and software are both successfully implemented.

 

Project Title Vehicle Speed Safety Alert and Control System: Digital Speed Vehicle Display System
Student Name Lai Poey Seng
Supervisor Mr Simon Lau Boung Yew
Year of Completion 2007
Description With the advancement of technology, cars are getting faster and more powerful. Car accidents are major concern today because of an increasing number of car fatalities. There are many factors that can lead to an accident and one of the main factors of accidents is human error. In the highway, where the roads are straight and the cars are traveling fast, a driver needs to adjust his own car speed to keep a safe distance with the car in front. The driverís judgment is subjective and varies among individuals. Sometime the subjective judgment might be wrong and this error may cause an accident if the driver is not able to stop the car in time. From this project, we seek to give the driver a relative value of speed so that the driver is able to make a more objective judgment of safety. If the driver misjudge, the project will warn the driver of potential danger. If no further action taken by the driver, the project can take control of the car by pressing the brake and remove the accelerator pedal. The objective of this project is to make a hardware prototype that may simulate and predict the behaviour of highway driving style. The hardware is equipped with ultrasonic sensor that is able to sense the car in front. The microcontroller acquires data from the sensor, processes the data and displays the speed of the car in front to the user. The project is aimed ultimately to be integrated into an auto alert system that is able to warn driver of danger if it detects abnormality of speed of the vehicle in front. The speed value of the driverís own vehicle speed and the speed of vehicle in front are to be displayed on a LCD. In order to create an alert system, the speed calculation of the car in front needs to be developed.

Results / Conclusion In this project, the hardware for the digital speed vehicle display system was built and tested. The hardware prototype is able to display speed values on the LCD and respond to switch user input. Both the driverís speed and speed of vehicle in front can be displayed on the LCD. This module was successfully integrated with the sensor module to obtain the distance value which is used to calculate the speed of vehicle in front. This hardware prototype is able to show a general concept for the vehicle speed safety alert system. This system is a good device that can be used to help reducing accidents on highways. The system in a way gives the driver a better judgment.